1. Field of the invention
The present invention relates to a microprocessor, and more specifically to a microprogram-controlled microprocessor capable of executing a block transfer instruction as a macro instruction.
2. Description of related art
A microprogram-controlled microprocessor (abbreviated or simply called "microprocessor" hereinafter) is configured so that a macro instruction which can be programmed by a user is processed by executing a corresponding microprogram, namely a series of microinstructions. Most microprocessors have a macro instruction which requires reading one or two items of data from a memory external to the microprocessor, and executing a designated operation for the read data, and then, writing the result of the operation to the memory external to the microprocessor.
For example, a typical conventional microprocessor includes a data controller for interfacing between the inside of the microprocessor and a data bus external to the microprocessor, and an execution controller for executing a required operation for data fetched from the external data bus. The data controller and the execution controller are coupled to each other through an internal data bus provided in the inside of the mircroprocessor.
The data controller includes first and second read operand registers and one write operand register, and the execution controller includes first and second temporary registers and an arithmetic and logic unit (ALU) for executing an arithmetic and logic operation on the basis of both or one of two items of data stored in the first and second temporary registers.
In operation, data is read from the external data bus and is temporarily held in the first or second read operand register of the data controller, so that two items of data temporarily held in the first and second read operand registers wait for the execution controller to fetch or read. When execution of a microprogram corresponding to a given operation instruction is started, the execution controller causes the first and second temporary registers to fetch the two items of data held in the first and second read operand registers, respectively, so that the ALU executes a designated operation for the two items of data held in the first and second temporary registers and a result of the executed operation is written into the write operand register of the data controller. In the case that the given instruction is a simple transfer instruction, it is not necessary to execute the operation through the intermediary of the ALU. However, the data is, without exception, transferred to the execution controller once and then returned to the data controller.
In the above mentioned conventional microprocessor, an instruction set includes a macro instruction called a "block transfer instruction". This block transfer instruction can be defined to be a macro instruction for transferring contents of continuous memory areas to different continuous memory areas. When the block transfer instruction is used, user is required to designate, as operands, a data transfer source address, information indicating to what extent from the data transfer source address the data should be transferred, namely, how many bytes counting from the data transfer source address should be transferred (this information will be called a "transfer source length" hereinafter), a data transfer destination address, and information indicating to what extent from the data transfer destination address the transfer data is written, namely, how many bytes counting from the data transfer destination address should be written with the transfer data (this information will be called a "transfer destination length" hereinafter). Incidentally, the number of bytes actually transferred in the block transfer instruction corresponds to a minimum value or a smaller one of the transfer source length and the transfer destination length. In addition, when the block transfer has been completed, two values obtained by adding the number of the actually data-transferred bytes to the transfer source length and the transfer destination, respectively, are stored in two predetermined registers.
In the case that the block transfer instruction is executed by a microprogram, the following processing is executed:
When execution of the microprogram is started, data stored in the memory is stored in the first read operand register of the data controller, and then, the block transfer instruction is executed in the following sequence:
Step 1: A transfer source address is set to a transfer source address holding register; PA1 Step 2: A transfer destination address is set to a transfer destination address holding register; PA1 Step 3: A minimum (smaller) value of the transfer source length and the transfer destination address is set to a loop counter; PA1 Step 4: If a content of the loop counter is zero, the microprogram is terminated, and if the content of the loop counter is not zero, the content of the loop counter is decremented by only one; PA1 Step 5: Data of one byte is fetched from the first read operand register and stored in the first temporary register so that a transfer operation is executed; PA1 Step 6: A result of the execution of the transfer operation is written into the write operand register; PA1 Step 7: The content of the transfer source address holding register is incremented by only one (additional operation) in order to designate a memory address to be next read; PA1 Step 8: The content of the transfer destination address holding register is incremented by only one (additional operation) in order to designate a memory address to be next written; PA1 Step 9: It returns to the Step 4,
As seen from the above, when the block transfer instruction is executed by the microprogram in the conventional microprocessor, both of the transfer source address holding register and the transfer destination address holding register have to be updated in each loop. In this case, a processing time per one transfer loop requires six clocks, assuming that each of the above mentioned Steps 4 to 9 can be executed with one clock. Actually, since some of the above mentioned Steps 4 to 9 can be simultaneously executed, the processing time per one transfer loop becomes about four clocks. Here, assume that a width of the data bus of the microprocsssor is four bytes, and the microprocessor has the capability capable of reading or writing one data unit (four byte at maximum) with two clocks.
As seen from the above, when the block transfer instruction is executed by the microprogram in the conventional microprocessor, one byte of data is transferred with four clocks. This means that only one-fourth of a bus transfer capability of the microprocessor is utilized. However, if the bus transfer capability of the microprocessor is utilized at maximum, it should be possible to transfer four bytes of data with four clocks, since four bytes of data can be read with two clocks and four bytes of data can be written with two clocks.
Turning to the steps of the data transfer processing as mentioned above, the data held in the first read operand register of the data controller must have been stored in the first temporary register of the execution controller without exception in the conventional microprocessor. In other words, since the transfer data has been transferred through the intermediary of the execution controller, namely, since the data transfer has been executed by using the microprogram, the number of clocks required for the data transfer of one transfer loop have become a hindrance in the data transfer. In order to obtain the maximum bus transfer capability in the block transfer instruction, it is necessary to complete one transfer loop with one clock. However, it is impossible to realize a one-clock transfer loop inasmuch as the microprogram is used.